The disclosed invention relates generally to clock-gating in an electronic chip, and in particular, to functional block level clock-gating.
Managing power consumption within an electronic chip has historically been and continues to be a major factor driving the design of chips within the semiconductor industry. As the number of transistors within chips (e.g., microprocessor, graphics chips) has increased, the need to reduce on-chip power consumption has increased and has become more difficult to achieve. The power consumption dilemma is further exacerbated by the increasing use of large, complex chip designs in mobile devices where low-power consumption is critical.
Power saving techniques, such as deactivating or slowing-down a clock signal to a large zone of a chip for the entire time that the chip is in a power savings mode, can be used to meet the low power consumption specifications of some chip designs. These known clock signal power saving techniques, however, have several drawbacks. For example, the latency to slow-down, turn-off, and/or turn-on a clock signal to a fixed zone when entering or exiting a power savings mode within a chip can be prohibitively long (e.g., hundreds of clock cycles) and can substantially disrupt data processing by the chip. Accordingly, a need exists for methods and apparatus for clock-gating within an electronic chip.